With the rapid development of semiconductor technology, the feature size of semiconductor structures is continuously reduced, and the integration level of integrated circuits (ICs) is steadily improved. Accordingly, the requirements on device performance are also becoming higher and higher.
Currently, with the dimension of metal-oxide-semiconductor field-effect transistor (MOSFET) continuously becoming smaller, in order to accommodate the reduction of the process node, the channel length in MOSFET devices may have to be reduced, which may be conducive to increasing the density of the chip, improving the switching speed of the MOSFET devices, etc.
However, as the channel length of devices decreases, the distance between the source region and the drain region may also be reduced. Therefore, the ability of the gate structure in controlling the channel may be degraded such that pinching off the channel by the gate may be more and more difficult. As such, the sub-threshold leakage phenomenon, i.e. the short-channel effect (SCE), becomes a crucial technical challenge and needs to be resolved.
In order to accommodate the requirements for scaling-down semiconductor devices, semiconductor process gradually switches from planar MOSFET devices to more efficient three-dimensional (3D) transistor devices, such as fin field-effect transistors (Fin-FETs). Fin-FET devices demonstrate desired ability in control the channels.
However, the electrical performance of the conventional semiconductor structures may still need to be improved. The disclosed semiconductor devices and fabrication methods thereof are directed to solve one or more problems set forth above and other problems in the art.